With the increase of volume of electronic data storages, also referred to as hardware memory storages, the number of storing procedure errors also increases. The endurance of the electronic data storage can be defined as the number of Program and Erase (P/E) cycles that each memory cell can tolerate throughout its lifetime. Single-level cell (SLC) NAND flash technology, being one of the mainstream NAND flash technologies, achieves 100,000 P/E cycles at 50 nm process node. Meanwhile, the migration of NAND flash technology from removable media storage to memory- and performance-intensive mobile computing devices, such as smart phones, tablets, notebooks, and so forth, is driving up NAND flash endurance requirements. While universal serial bus (USB) flash drives and micro secure digital (microSD) memory cards, which comprised the core NAND market segments until recently, need only a few hundred P/E cycles, the NAND flash embedded in smart phones typically requires at least 3,000 P/E cycles. Enterprise-grade solid-state drives (SSD) require as much as 50,000 P/E cycles. However, the endurance of the hardware memory storage can be severely degraded in the course of P/E cycles due to process and array impairments, resulting in a nonlinear increase in the number of errors in the hardware memory storage.
The most common approach to combating endurance limitations is the use of an error correction code (ECC). The ECC utilizes data checking and correction bits, also referred to as parity bits, which are stored on the NAND flash memory in addition to the application content, also referred to as data bits. For the ECC to correct more bits, more parity bits needs to be stored, resulting in additional cost. Furthermore, an ECC scheme is usually characterized by the code rate, which is defined as a ratio between the number of data bits to the total number of stored bits (data+parity). Higher code rate is more cost-effective but typically yields weaker correction capability and is therefore more sensitive to errors.
The ECC schemes are capable of correcting more bits for a given code rate, such as irregular Low-Density Parity-Check (iLDPC) codes. However, a typical iLDPC algorithm is designed for data transmission channels rather than for electronic data storages. Furthermore, decoding algorithms for the iLDPC codes may use huge matrices dimensions resulting in complexity of matrix computations. Additionally, even the most modern and efficient ECC schemes are not effective when the number of errors is too large.